Bus Minimization and Scheduling of Multi-chip Modules

Multi-Chip Module design is an increasingly common design style for integrated circuits. The area taken up by buses in a multi-chip module design has a signiicant eeect on the size of the circuit. This paper considers several diierent methods that reduce the required number of buses. Two models of interchip communication are studied. The rst, called immediate transfer, requires that all values are transferred between chips as soon as they are computed. The second, called exible transfer, allows values to be transferred any time between when they are computed and when they are used. Using the immediate transfer model, it is shown that integer linear programming can be used to obtain a schedule that minimizes the number of functional units as well as the number of buses. Next, using the exible transfer model, an eecient polynomial time algorithm that calculates the minimum number of buses needed given a particular schedule is designed. Finally, we present three heuristics for the exible transfer model that attempt to minimize the number of buses during scheduling. Experimental results are shown that illustrate the eeciency of the algorithms as well as the savings achieved.